SWTest Asia has SOLD OUT!
We have reached our maximum registration capacity and all deadlines have passed. We can no longer accept new registrations or substitutions. No on-site registrations will be accepted.
定員に達しましたので受付を終了させていただきました。心より感謝申し上げます。
現地会場での参加登録はお受けできませんのでご了承ください。
The 2026 program will be updated with more details in late August 2026.
Last updated:
Schedule-At-A-Glance
subject to change
For details on the schedule for the 6th Annual Golf Tournament on Saturday, November 7, please visit the golf webpage.
Attendee Registration Check-In will be from 8:00 to 17:00 on both Thursday and Friday.
Thursday, November 5
Friday, November 6
Detailed Technical Session Schedule
Wednesday, November 19
[table “10” not found /]
Thursday, November 20
| Time | Event | Additional Detail |
|---|---|---|
| 05:00 | Board Bus at Sheraton Hsinchu | Players gather in the hotel lobby to board the charter bus |
| 05:15 | Bus Leaves Sheraton Hsinchu | Bus departs promptly for the Royal Kuan Hsi Golf Club |
| 06:00 | Arrive at Royal Kuan Hsi Golf Club | |
| 06:10 | Pro Shop Patio Registration Opens | Teams check in and pick up boxed breakfasts |
| 06:30 | Mandatory Check-in Cutoff | All players must complete registration by 6:30 |
| 06:50 | Tee Time (Scramble Format) | |
| 11:30 | Play Completed & Hot Springs Spa | 18 holes completed; complimentary hot springs spa access |
| 12:00 | Cocktail Reception | Networking reception at the Clubhouse |
| 12:30 | Lunch & Awards Banquet | Post-tournament awards banquet and lunch |
| 14:30 | Bus Leaves for Sheraton Hsinchu | Bus departs golf course for the return trip |
| 15:10 | Bus Arrives at Sheraton Hsinchu |
Poster Session
Session Chair: Nyi Nyi THEIN (Sandisk Corporation – Japan)
- Evaluation of Palladium Alloy Probe with Suppressed Sn Diffusion Reaction
Kenichi SATO, Tomohisa HOSHINO, Naohito ODANI (Yokowo Corporation – Japan), Shohji IKUO (Graduate School of Science and Technology, Gunma University – Japan) - Technologies to support data transmission with extremely high frequencies (400G+) on printed circuit boards
Quaid Joher FURNITUREWALA (Advantest America Inc – USA) - High Voltage DUT Power Supply IC for Automotive Grade Testing
Thomas ABIOG (Elevate Semiconductor – USA) - A Modern Low Current, Low Leakage Switch Matrix
Hai DAU, Israel ECHEVARRIA, John WILLIAMSON, Christine BUI (Spire Manufacturing, Inc. – USA) - A POGO-Type MEMS pin for Fine-Pitch Probing
Jong-Uk BU, Ho-Sub BANG, Hwangsub KOO, SangHyeop LEE, Seo KOO, Seokhwan YOO, Youngho NAM (WithMEMS – South Korea) - Applying Chiplet Concepts to Interfaces: Breaking the Barriers Holding the Industry Down
Eric SHOEMAKER, Brian BRECHT (DIS Tech – USA) - Innovative Testing Strategies for Silicon Photonic Devices in Engineering and Production Applications
Kainoa KEKAHUNA (FormFactor – USA) - Evaluation of Ultra-High-Multi Layer PCB (124L) for Probe Card
Yasuyuki SHINBO, Toshihiko OGURA (OKI Circuit Technology Co., Ltd. – Japan) - High Pin Count, High Parallelism Vertical Probe Card Characterization Strategies for HVM Automotive Bump Wafer Testing
Cameron HARKER (FormFactor – USA), Yoichi URAKAWA (FormFactor – Japan) - Reinventing Guide Plates for Vertical Probe Cards: Solving Design Constraints with Advanced Laser Drilling and Materials Science
Chris STOKES (Oxford Lasers – United Kingdom) - From Concept to Extended Validation: Localized Thermal Management for AI and GPU Wafer Testing
Klaudiusz HOLECZEK (Watttron GmbH – Germany), Klemens REITINGER (ERS electronic GmbH – Germany) - Development of low CTE LTCC material for ST substrates
Yasuo YAMAZAKI, Eiichi NAKAMURA, Shigekatsu KONO, Takahisa YAMAGUCHI (Nippon Electric Glass Co., Ltd. – Japan) - Combining Material Development & Advanced Processing into High-Quality Foils to optimize application performance and cut costs
Matthias WEGNER, Martin SENZEL, Nail AKROUTI (Heraeus Precious Metals – Germany) - Delay Characterization for FPGA PUFs Using Fully Synchronous On-Chip PLL Techniques
Kentaroh KATOH, Toru NAKURA (Fukuoka University – Japan), Haruo KOBAYASHI (Gunma University – Japan) - Automated Cause-Effect Discovery on Multivariate Time-series Data -Semiconductor production dynamics and process anomaly
ChenDing MAO, Ke LI (University of Tsukuba – Japan) - Multi-criteria Parameter Optimization for Complex Systems – Multi-Objective Scheduling Case
ChenDing MAO, Hiroto AKIZUKI, Shoyo YOSHIDA (University of Tsukuba – Japan) - J-OSAT Promotion
Akio TSUNOI, Tsuyoshi YOKOYAMA (Tera Probe – Japan)
Friday, November 21
[table “12” not found /]
Poster Session
Session Chair: Nyi Nyi THEIN (Sandisk Corporation – Japan)
- Evaluation of Palladium Alloy Probe with Suppressed Sn Diffusion Reaction
Kenichi SATO, Tomohisa HOSHINO, Naohito ODANI (Yokowo Corporation – Japan), Shohji IKUO (Graduate School of Science and Technology, Gunma University – Japan) - Technologies to support data transmission with extremely high frequencies (400G+) on printed circuit boards
Quaid Joher FURNITUREWALA (Advantest America Inc – USA) - High Voltage DUT Power Supply IC for Automotive Grade Testing
Thomas ABIOG (Elevate Semiconductor – USA) - A Modern Low Current, Low Leakage Switch Matrix
Hai DAU, Israel ECHEVARRIA, John WILLIAMSON, Christine BUI (Spire Manufacturing, Inc. – USA) - A POGO-Type MEMS pin for Fine-Pitch Probing
Jong-Uk BU, Ho-Sub BANG, Hwangsub KOO, SangHyeop LEE, Seo KOO, Seokhwan YOO, Youngho NAM (WithMEMS – South Korea) - Applying Chiplet Concepts to Interfaces: Breaking the Barriers Holding the Industry Down
Eric SHOEMAKER, Brian BRECHT (DIS Tech – USA) - Innovative Testing Strategies for Silicon Photonic Devices in Engineering and Production Applications
Kainoa KEKAHUNA (FormFactor – USA) - Evaluation of Ultra-High-Multi Layer PCB (124L) for Probe Card
Yasuyuki SHINBO, Toshihiko OGURA (OKI Circuit Technology Co., Ltd. – Japan) - High Pin Count, High Parallelism Vertical Probe Card Characterization Strategies for HVM Automotive Bump Wafer Testing
Cameron HARKER (FormFactor – USA), Yoichi URAKAWA (FormFactor – Japan) - Reinventing Guide Plates for Vertical Probe Cards: Solving Design Constraints with Advanced Laser Drilling and Materials Science
Chris STOKES (Oxford Lasers – United Kingdom) - From Concept to Extended Validation: Localized Thermal Management for AI and GPU Wafer Testing
Klaudiusz HOLECZEK (Watttron GmbH – Germany), Klemens REITINGER (ERS electronic GmbH – Germany) - Development of low CTE LTCC material for ST substrates
Yasuo YAMAZAKI, Eiichi NAKAMURA, Shigekatsu KONO, Takahisa YAMAGUCHI (Nippon Electric Glass Co., Ltd. – Japan) - Combining Material Development & Advanced Processing into High-Quality Foils to optimize application performance and cut costs
Matthias WEGNER, Martin SENZEL, Nail AKROUTI (Heraeus Precious Metals – Germany) - Delay Characterization for FPGA PUFs Using Fully Synchronous On-Chip PLL Techniques
Kentaroh KATOH, Toru NAKURA (Fukuoka University – Japan), Haruo KOBAYASHI (Gunma University – Japan) - Automated Cause-Effect Discovery on Multivariate Time-series Data -Semiconductor production dynamics and process anomaly
ChenDing MAO, Ke LI (University of Tsukuba – Japan) - Multi-criteria Parameter Optimization for Complex Systems – Multi-Objective Scheduling Case
ChenDing MAO, Hiroto AKIZUKI, Shoyo YOSHIDA (University of Tsukuba – Japan) - J-OSAT Promotion
Akio TSUNOI, Tsuyoshi YOKOYAMA (Tera Probe – Japan)