SWTest Asia has SOLD OUT!
We have reached our maximum registration capacity and all deadlines have passed. We can no longer accept new registrations or substitutions. No on-site registrations will be accepted.
定員に達しましたので受付を終了させていただきました。心より感謝申し上げます。
現地会場での参加登録はお受けできませんのでご了承ください。
The 2026 program will be updated with more details in late August 2026.
Last updated:
Schedule-At-A-Glance
subject to change
For details on the schedule for the 6th Annual Golf Tournament on Saturday, November 7, please visit the golf webpage.
Attendee Registration Check-In will be from 7:30 to 17:00 on both Thursday and Friday.
Thursday, November 5
Friday, November 6
Detailed Technical Session Schedule
Wednesday, November 4
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Thursday, November 5
| Time | Event |
|---|---|
| 7:30 – 17:00 | Conference Registration Check-In |
| 8:00 – 9:30 | EXPO Move-In/Setup |
| 8:45 – 9:15 |  Welcome to SWTest Asia 2026Jerry BROZ, PhD (SWTest Conference General Chair – USA) |
| 9:15 – 10:00 |  VISIONARY KEYNOTE (more details)Title TBD Konrad YOUNG, PhD Adjunct Professor (National Taiwan University Leadership Program – Taiwan) Former R&D Director (TSMC – Taiwan) |
| 10:00 – 10:30 | Tea Break in EXPO Hall |
| 10:00 – 10:30 | Technical Poster Session |
| 10:00 – 17:30 | SWTest Asia 2026 EXPO Open |
| 10:30 – 12:00 | Technical Session 1: Silicon Photonics and Co-Packaged Optics Session Chair: Alan FERGUSON (Oxford Lasers – UK) |
| 10:30 – 11:00 |  Technical Challenges in Multi-Stage Test Insertions (Insertion 1-4) and Their Application in Heterogeneously Integrated Silicon Photonics and Co-Packaged Optics (CPO)Clark LIU (MJC Taiwan – Taiwan), Dr. San-Liang LEE (HiSPA / NTUST – Taiwan) |
| 11:00 – 11:30 |  Integrated Silicon Photonics Turn-key HVM Solution for AI Infrastructure AstraCore Systems (ACS) Hevin YU (SURUGA SEIKI TAIWAN BRANCH – Taiwan), Dr. CL (AstraCore System – Taiwan) |
| 11:30 – 12:00 | Closing the Lab to Fab Correlation Gap in Silicon Photonics Wafer Test Alejandro BURITICA (FormFactor – USA) |
| 12:00 – 14:00 | LUNCH in EXPO Hall & EXPO Foyer |
| 12:25 – 12:45 | Tech Showcase 1 – Company TBD Title: TBD |
| 12:55 – 13:15 | Tech Showcase 2 – Company TBD Title: TBD |
| 13:25 – 13:45 | Tech Showcase 3 – Company TBD Title: TBD |
| 14:00 – 15:30 | Technical Session 2: Test Systems and Characterization Session Chair: Alex YANG (MPI Corporation – Taiwan) |
| 14:00 – 14:30 |  Leveraging an ATE Design Architecture Concept for Same-Channel, Multi-Methodology Device Characterization with Integrated SMU, CMU, and PIV ResourcesJosh WU, Julie LE (Chroma ATE – USA) |
| 14:30 – 15:00 | Evaluating SiPh Wafer Tester Performance Using an Adapted Measurement-System Analysis Framework JEFFREY LAM, Qingshan YAN, Tianyi GU (CompoundTek – Singapore) |
| 15:00 – 15:30 |  AI-Driven Failure Prediction and Lifetime Extension in Semiconductor Test HardwarePradeep SELLAMUTHU, Bharath Kumar VENKATACHALAM (Caliber Interconnects – India) |
| 15:30 – 16:00 | Tea Break in EXPO Hall |
| 15:30 – 16:00 | Technical Poster Session |
| 15:35 – 15:55 | Tech Showcase 4 – Company TBD Title: TBD |
| 16:00 – 17:30 | Technical Session 3: AI, HPC Test Session Chair: Joey WU (Toward Technologies – Taiwan) |
| 16:00 – 16:30 |  Advancing HPC Wafer-Level Testing Through Sacrificial Pad Probing and MEMS Vertical Probe TechnologyAlan LIAO (FormFactor – USA), Nawman WU (Keystone MicroTech Taiwan – Taiwan) |
| 16:30 – 17:00 |  Enabling Reliable Wafer-Level Test of HPC Devices Through Probe Hardware Protection, Power-Aware Test Architecture, and Design Co-OptimizationMin Ting HAN, Shi Kang CHIN (Microsoft – Malaysia) |
| 17:00 – 17:30 |  3x Power Delivery at Probe for AIDon THOMPSON (PTSL – USA) |
| 17:30 – 18:30 | Welcome Reception in EXPO Hall |
Poster Session
Session Chair: Patrick MUI (JEM America – USA)
- Parametric Test Solutions for High-Yield Panel Interposer Manufacturing in AI Applications
Kenichi TAKANO (Keysight Technologies – Japan) - A High-Speed and High-Throughput Per-Pin Parametric Measurement Architecture for Advanced Semiconductor Reliability Testing
Tomotaka HOSOTANI, Daiki IWASAKI, Katsuhito IWASAKI, Taro KORESAWA (Keysight Technologies – Japan) - Predicting Physical Failure Analysis Success Rate Using Machine Learning Method on Wafer Sort Memory Bitmap Failure Data
Patrick Yin Hong CHAN, Chen CHANGQING, Murugan SANJAY ARAVIN (Globalfoundries – Singapore) - Advanced LTCC Technology for High-Performance 12-Inch MLC in Wafer Test Applications
Takahisa YAMAGUCHI, Kono SHIGEKATSU, Yamazaki YASUO (Nippon Electric Glass Co.,Ltd. – Japan) - Lowering Cost of Ownership- From Advanced CMOS Manufacturing to Future Quantum Wafer Characterization
Ching Too CHEN, Julie LE (Chroma ATE, Inc. – USA) - Zone-Specific Customized Silicon Guide Plates for Co-Optimizing CCC and Signal Integrity
Young Ho NAM, Hwang Sub KOO, Seo KOO, Jong BU (WithMEMS – South Korea) - Wafer probing with integrated functional device test by magnetic stimulation
Georg FRANZ (T.I.P.S. Messtechnik GmbH – Austria) - Ultra-Fine-Pitch Conductive Rubber Socket for HBM and AI Chiplet Testing
Jeongmin SEO (Hanyang University – South Korea), Chloe S. KIM (Everitt Inc. – South Korea), Yei Hwan JUNG (Hanyang University, Everitt Inc. – South Korea) - A HW or SW approach to Power Supply Rail Multi Switching on a Device Power Supply
Thomas ABIOG (Elevate Semiconductor – USA)
Friday, November 6
| Time | Event |
|---|---|
| 7:30 – 17:00 | Conference Registration Check-In |
| 8:45 – 9:00 | Friday Program Overview Jerry BROZ, PhD (SWTest Conference General Chair – USA) |
| 9:00 – 10:00 | Technical Session 4: AI-Enabled Test Operations Session Chair: Clark LIU (MJC Taiwan – Taiwan) |
| 9:00 – 9:30 |  AI-Driven Semiconductor Capacity ConstraintsBoris METODIEV (TechInsights – United Kingdom) |
| 9:30 – 10:00 | “From Reactive to Predictive: Next-Generation Multi-Modal AI and Edge Computing in Advanced Semiconductor Testing ECMS + Edge AI + Agent” Po-Hao HUANG (WEILI Technology – Taiwan) |
| 10:00 – 10:30 | Tea Break in EXPO Hall |
| 10:00 – 10:30 | Technical Poster Session |
| 10:00 – 16:00 | SWTest Asia 2026 EXPO Open |
| 10:05 – 10:25 | Tech Showcase 5 – Company TBD Title: TBD |
| 10:30 – 12:00 | Technical Session 5: HBM and Advanced Package Testing Session Chair: Eric Chia-Cheng CHANG (Intel – USA) |
| 10:30 – 11:00 | Solder-Free Micro Coaxial Spring Probes for Advanced-Package Test: Fluxless Fine-Spot Laser Weld Characterization and an Automated Eight-Station Assembly Platform Song Jhe LIU (Pioneer Probe Pins Technology Co., Ltd. – Taiwan) |
| 11:00 – 11:30 |    Data-Driven Post-Silicon Validation Framework for High Bandwidth Memory in 2.5D Integration: Adaptive Stress Testing and Hierarchical Fault IsolationJayasurya MOORTHY, Kalyana Sundaram CHANDRAN, Senthilkumar DHAMODHARAN (Caliber Interconnect Solution Pvt Ltd – India) |
| 11:30 – 12:00 | The Road from 16 to 3000 DUT DRAM Test – A historic review Michael HUEBNER (Huebner Test Consulting – Germany) |
| 12:00 – 14:00 | LUNCH in EXPO Hall & Foyer |
| 12:25 – 12:45 | Tech Showcase 6 – Company TBD Title: TBD |
| 12:55 – 13:15 | Tech Showcase 7 – Company TBD Title: TBD |
| 13:25 – 13:45 | Tech Showcase 8 – Company TBD Title: TBD |
| 14:00 – 15:30 | Technical Session 6: Reliability and High-Volume Manufacturing Session Chair: Nyi Nyi THEIN (Sandisk Corporation – Japan) |
| 14:00 – 14:30 |  CRES Methodology for Cost-Efficient Reliability in Wafer-Level Testing: A Novel CRES-Based Approach to Prevent Pin Degradation and Burn in Ganged High-Current Power RailsDaniel ONG, Chong Yih KHOO, Nicholas LEOW, Vemuri VENKAT (Microsoft – Malaysia) |
| 14:30 – 15:00 | High-Density Laser Drilling in Semiconductor Test Hardware: Evaluating the Trade-Off Between In-House Capability and Outsourced Manufacturing Alan FERGUSON, Chris STOKES (Oxford Lasers – United Kingdom) |
| 15:00 – 15:30 |  Universal Hybrid Cleaning for Vertical to Microcantilever MEMS Probe under Low and High-Temperature HVM Test Victoria TRAN (Gel-Pak – USA), Tomonao NAKASIMA (Japan Electronic Materials – Japan) |
| 15:30 – 16:00 | Tea Break in EXPO Hall |
| 15:30 – 16:00 | Technical Poster Session |
| 16:00 – 17:00 | EXPO Move-out |
| 16:00 – 17:30 | Technical Session 7: Thermal Management and High-Speed RF Session Chair: Jerry BROZ (SWTest Conference General Chair – USA) |
| 16:00 – 16:30 |  Probe card design challenges for High frequency testingKenta OE (Japan Electronic Materials Corp. – Japan) |
| 16:30 – 17:00 |  Power dissipation to reduce or isolate the PCB from temperature area and power dissipation at AI probe head with liquid coolingStefan THURMAIER (Turbodynamics GmbH – Germany) |
| 17:00 – 17:30 |  Enabling >112GHz RF Probe Solutions for 448G PAM4 Datacenter CommunicationsChristopher LEMOINE (FormFactor Inc. – USA), Daniel BOCK (Cascade Microtech – USA) |
| 17:30 – 17:45 | Technical Awards Presentation |
| 17:45 – 19:00 | Taiwan Street Food Festival |
Poster Session
Session Chair: Patrick MUI (JEM America – USA)
- Parametric Test Solutions for High-Yield Panel Interposer Manufacturing in AI Applications
Kenichi TAKANO (Keysight Technologies – Japan) - A High-Speed and High-Throughput Per-Pin Parametric Measurement Architecture for Advanced Semiconductor Reliability Testing
Tomotaka HOSOTANI, Daiki IWASAKI, Katsuhito IWASAKI, Taro KORESAWA (Keysight Technologies – Japan) - Predicting Physical Failure Analysis Success Rate Using Machine Learning Method on Wafer Sort Memory Bitmap Failure Data
Patrick Yin Hong CHAN, Chen CHANGQING, Murugan SANJAY ARAVIN (Globalfoundries – Singapore) - Advanced LTCC Technology for High-Performance 12-Inch MLC in Wafer Test Applications
Takahisa YAMAGUCHI, Kono SHIGEKATSU, Yamazaki YASUO (Nippon Electric Glass Co.,Ltd. – Japan) - Lowering Cost of Ownership- From Advanced CMOS Manufacturing to Future Quantum Wafer Characterization
Ching Too CHEN, Julie LE (Chroma ATE, Inc. – USA) - Zone-Specific Customized Silicon Guide Plates for Co-Optimizing CCC and Signal Integrity
Young Ho NAM, Hwang Sub KOO, Seo KOO, Jong BU (WithMEMS – South Korea) - Wafer probing with integrated functional device test by magnetic stimulation
Georg FRANZ (T.I.P.S. Messtechnik GmbH – Austria) - Ultra-Fine-Pitch Conductive Rubber Socket for HBM and AI Chiplet Testing
Jeongmin SEO (Hanyang University – South Korea), Chloe S. KIM (Everitt Inc. – South Korea), Yei Hwan JUNG (Hanyang University, Everitt Inc. – South Korea) - A HW or SW approach to Power Supply Rail Multi Switching on a Device Power Supply
Thomas ABIOG (Elevate Semiconductor – USA)