More details coming soon!
Thursday Keynote Speaker
Wei-Chung Lo, PhD
Deputy General Director
Electronic and Optoelectronic System Research Laboratories (EOSL)
Industrial Technology Research Institute (ITRI)
Dr. Wei-Chung (Robert) Lo is currently the Deputy General Director of Electronic and Optoelectronic System Research Laboratories (EOSL). Dr. Lo joined Industrial Technology Research Institute to work in advanced electronic packaging, such as WLP, 3D IC/3D stacking, fan-out, heterogeneous integration technology for more than 20 years, 85 papers and 40 patents granted.
Dr. Lo received his MS and PhD degrees from National Taiwan University and is an alumnus of the University of Pennsylvania Wharton Business School AMP program. Dr. Lo serves as TWG chair of IoT Chapter of IEEE Heterogenous Integration Roadmap (HIR). He has been actively involved with IEEE and iMAPS working with various Interconnect Committees. Currently, he is the Chairman of International Microelectronics Assembly and Packaging Society (IMAPS)-Taiwan Chapter and is the Co-Chair of SEMI Packaging and Test committee as well as a Tech Consultant/Committee member of TPCA.
Advanced Electronic Heterogeneous Integration and Testing
Next wave of semiconductor is going to be two major trends, one is feature size scaling (more Moore) and the other is system scaling/heterogeneous integration (More than Moore). The presentation is to share the key aspects of future applications in semiconductor era: High frequency (Beyond 5G or 6G), High speed/HPC (AI chips or High-performance computing) and High power applications. We believe that the semiconductor IC will keep the momentum to speed up the market-oriented research and development to fulfill the domain needs of smart living, quality of life and sustainable environment by adopting advanced semiconductor technology.
The up-to-date results and development of WBG semiconductor (eg. GaN & SiC) as well as Si-based advance AI-related devices based on heterogeneous integration (side- by-side or 3D stacking) will be highlighted. The challenge of testing multiple dies through the limited interconnect will also be discussed including but not limited to the new test board, equipment, and methodologies.
Friday Keynote Speaker
Vice President of Memory Product Solutions
Western Digital, Inc.
Pradip Ghimire believes there is a tremendous value creation at the intersection of technology development and high-volume manufacturing through Engineering innovations.
Over the past 20 plus years, Pradip has been at the forefront of leading NAND, ASIC, and DRAM based products from technology definition to high volume manufacturing. Currently, he serves as the Vice President of Memory Product Solutions at Western Digital, responsible for NAND productization and manufacturing testing for entire WD flash product portfolio. Pradip has held leadership positions at Micron and SanDisk in product Engineering prior to Western Digital.
Pradip holds a Bachelor’s Degree in Electrical Engineering from Montana State University. He has completed Stanford Executive program and is an alumnus of Stanford Graduate School of Business.
During his free time in California, USA, he enjoys reading about philosophy and technology, basketball, and spending time with his family.
Wafer in, SSD out – Famous Last Words of a Test engineer to Manufacturing: “Test All Bits!”
3D NAND technology has made significant advancements, progressing from only a few cell layers to today’s impressive 3D skyscraper-like designs with hundreds of layers. This allows rapid growth in bit density, gross die per wafer and large flash capacity enablement from mobile phones to data centers and reduce the overall cost of the product so the world can store more data at a reasonable cost.
The technology advancement has also created an immense complexity in how we do manufacturing test from wafer level all the way to the final SSD product, which is a crucial process to ensure product quality and customer compliance. However, it also drives to higher CapEx investment, longer cycle time, increased factory space requirement, and yield loss. The industry is adapting multi-dimensional approaches to overcome these challenges.
During this keynote address, we will explore into the future of factory automation, sustainability, and the advantage of vertically integrated model from wafer-in to SSD-out. We will delve into the challenges faced in future high-volume NAND manufacturing testing and share our proactive approach to address these challenges through talented Engineers.