2026 Tech Showcase

Thursday, November 5

• Tech Showcase #1
  12:25 – 12:45
  ENLI TECHNOLOGY
  Spectral Imaging–Based Optical Loss Mapping for Efficient Failure Analysis and Wafer-Level Screening of Silicon Photonic Integrated Circuits (PICs)
  Details: As Silicon Photonics (SiPh) advances in Co-Packaged Optics (CPO) and high-speed communications, efficient Photonic Integrated Circuit (PIC) testing and failure analysis become increasingly critical. This study introduces a spectral imaging–based optical measurement technique that visualizes light propagation and maps optical loss within waveguides. Featuring submicron spatial resolution and picowatt-level sensitivity, the method enables rapid wafer-level and die-level defect localization, revealing scattering caused by structural irregularities and sidewall roughness. Integrated with Optical Wafer Acceptance Testing (OWAT), this approach significantly reduces testing time while improving throughput and enabling early identification of defective dies. Correlation with SEM, FIB, and 3D tomography further enhances failure analysis and understanding of complex optical behaviors. By combining high-resolution optical imaging, multi-wavelength analysis, and efficient defect screening, this technology provides a scalable solution for PIC characterization, process optimization, and reliability assessment, supporting next-generation silicon photonics manufacturing and large-scale CPO deployment.
  
• Tech Showcase #2
  12:55 – 13:15
  MPI Corporation
  The Next Era of High-Speed & Photonic Testing
  Details: Enabling 448G Connectivity and Double-Side CPO Testing for Next-Generation AI Infrastructure
  
• Tech Showcase #3
  13:25 – 13:45
  FormFactor, Inc.
  From GPU to HBM and CPO: Advancing Wafer Test for the AI Era
  Details: The rapid growth of AI is transforming the data center, as AI server racks integrate GPUs, XPUs, HBM, high-speed networking ICs, and optical connectivity into increasingly powerful computing platforms. Many of these devices rely on heterogeneous integration, chiplet architectures, and advanced packaging, which adds complexity and increases demand for wafer-level testing.
  These trends also create new test challenges, including extreme power delivery and current requirements, thermal management, finer-pitch probing, higher data rates with tighter signal-integrity demands, and co-packaged optics (CPO) that require combined electrical and optical testing. This presentation highlights FormFactor’s leadership in developing advanced probe card technologies and wafer test solutions that address these leading-edge challenges and enable the next generation of AI/HPC devices.
  
• Tech Showcase #4
  15:35 – 15:55
  Oxford Lasers, Ltd.
  200 Million Holes Later: What Manufacturing Data Is Teaching Us About the Future of Laser Micromachining
  Details: This presentation showcases the latest laser micromachining technologies being applied by Oxford Lasers, including advanced drilling, micro-structuring and precision material processing in glass, ceramics, metals and semiconductor substrates. Application examples will demonstrate how evolving customer requirements are driving the need for greater precision, higher throughput and enhanced process flexibility.
  

Friday, November 6

• Tech Showcase #5
  12:25 – 12:45
  MAXONESEMI
  Challenges in High-Speed CP Probe Card and WLBI Testing for the AI Era
  Details: As die sizes approach the reticle limit and AI accelerator power exceeds 1,000W, Chiplet and heterogeneous integration are becoming essential to overcome monolithic design limitations.The integration of multiple compute dies, HBM stacks, and interface dies significantly increases post-packaging test costs, making Known Good Die (KGD) and wafer-level screening critical.This shift drives growing demand for high-speed probe cards and dedicated Wafer-Level Burn-In (WLBI) solutions.
  
• Tech Showcase #6
  12:25 – 12:45
  TAIWAN MJC CO., LTD
  HBM Growth, AI Demand, and the Rising Complexity of Wafer‑Level Test
  Details: HBM demand is accelerating as AI training and inference workloads push memory bandwidth and capacity requirements to new levels. This growth is reshaping wafer‑level test, where larger I/O arrays, finer pitches, higher thermal density, and tighter cycle‑time expectations are creating significant engineering challenges. The session outlines how AI adoption is driving HBM scaling, the resulting complexity in probe design and test parallelism, and the key bottlenecks emerging across the test floor. It concludes with a forward look at future trends in HBM test readiness, including design‑for‑probe concepts, advanced contact technologies, and the shift toward higher‑efficiency test architectures.
  
• Tech Showcase #7
  12:55 – 13:15
  TBD
  
• Tech Showcase #8
  13:25 – 13:45
  JEM Taiwan
  JEM – Your Probing Partner for the Next Innovation
  Details: JEM’s electrical and structural engineers share the technical challenges they face as probe cards are pushed to their limits by increasing power density and shrinking pad pitch driven by AI demand. This isn’t a panel discussion — it’s a real look at how engineers from different disciplines see the same problems differently. As your probing partner, we’d love to explore what’s next together with you.