More details will be available in August 2025
Thank you to our Keynote Speakers from SWTest Asia 2025!
Thursday Keynote Speaker
Kazuyuki IWAGURO
Vice President of HPC Business Management and Operations Division
Renesas Electronics Corporation – Japan
Kazuyuki Iwaguro is the Vice President of HPC Business Management and Operations Division, Renesas Electronics Corporation. Since joining the company in 1994, he has been mainly engaged in development of Automotive MCU. Since 2018, he had managed testing technology and Lifetime Management team. In 2023, he became VP of Digital Operation Division, which is responsible for Test PF (management of Test Platform specification, Bigdata analytics tech and yield improvement method) and LMT (management of product delivery, cost improvement and quality) with MCU and SOC.
Keynote Topic:
Leading edge test technology and strategy for Automotive products
Renesas Electronics offers a cutting-edge lineup of automotive MCUs(Microcontrollers) and SOCs(System on Chip) that serve as the technological backbone for next generation vehicle systems. These products are highly regarded in the global market for their role in enabling electrification, intelligence, and connectivity in modern vehicles. Renesas Electronics continues to evolve its proprietary testing technologies and strategic quality management methods to support the competitiveness of its automotive MCUs and SoCs. Renesas Electronics has developed distinct and optimized testing strategies for its automotive MCUs and SoCs, each addressing unique technical challenges. By understanding the differences between these product categories and applying specialized testing approaches, Renesas achieves both high quality and cost efficiency across its portfolio. In this presentation, we will show the balancing cost competitiveness and quality for MCU testing and addressing complexity and high performance for SOC testing and we’ll discuss the challenge and expectations.
Friday Keynote Speaker
Atsuhiko OHNO
Distinguished Engineer
Technology Department #5 (Wafer/Package Test), Engineering Center
Rapidus Corporation
Atsuhiko Ohno received his Bachelor of Engineering in Electronic Engineering from Aichi Institute of Technology in 1984. He began his career in the semiconductor industry at ANDO Electric Corporation, an ATE supplier, where he spent 19 years in test system engineering and marketing. In 2003, he joined Elpida Memory (now Micron Memory Japan), where he managed DRAM product engineering to support low-power DRAM customers. In 2022, he moved to Micronics Japan Corporation as a marketing manager for logic probe cards. In 2023, Ohno joined Rapidus Corporation, where he currently serves as Distinguished Engineer and leads the logic testing team.
Keynote Topic:
Rapidus Initiatives and Logic Testing Challenges in Advanced Semiconductor Manufacturing
Presentation Outline:
- Semiconductor industry status
- AI GPU/CPU market update
- Who is Rapidus?
- Rapidus IIM (Innovative Integration for Manufacturing)/RCS (Rapidus Chiplet Solution) status
- Rapidus Logic testing challenges
- Vision and Key messages
Friday Keynote Speaker
Tetsu Ozawa
Socionext Inc. – Japan
Tetsu Ozawa is the General Manager of the Production & Quality Management Group, Product Engineering Division, at Socionext Inc. Headquarters in Yokohama city, Kanagawa prefecture, Japan. His team is responsible for testing technologies and yield management for all products of Socionext.He has more than 30 years of experience in test development and test engineering and is currently responsible for test management (technologies, quality, costs, equipment, components, capabilities, delivery dates, resources). Since then, he has been involved in the outsourcing business for IDM company and fabless company for over 15 years, and now as fabless, he has win-win relationship with global eco-partners to run the outsourcing business. Socionext will continue to provide stable supply of leading-edge, high-quality SoC products to global customers through superior testing technology.
Keynote Topic:
New Wafer Testing Challenges for Leading-Edge SoC Products
Socionext has built a new business model “Solution SoC” to provide SoC products to global customers seeking leading-edge and innovative chips. Socionext is focusing business on the advanced custom chips in the automotive, data center/networking and smart device markets. At present, in the leading-edge semiconductor market, with the evolution of the advanced wafer process node, enlargement of the device, increasing high-current, and high-speed rapid advance are crucial. In addition, leading-edge chips and packaging technologies are constantly developing, further increasing the value added to chips and assemblies.
We believe that the expectation and importance of advanced testing technology are more profound than ever, and that we are in a period of great change. We also believe that the establishment of new testing technologies and the linkage of new semiconductor value chains will bring significant benefits, such as improved yield and quality. In addition, it is necessary for us to adapt to flexible semiconductor process flows to make profits in various advanced products in the future. Therefore, we are promoting the establishment of a technology to change the test in real time according to the manufacturing situation and to shift the process flow to the left or right. Among these activities, wafer testing is very significant.
In this article we will introduce the development status of Socionext’s leading-edge SoC, and new test technology issues and the contents of the challenges, situation, and the expectation to the test partners countries.