Chen-Fu Chien, Ph.D.
Tsinghua Chair Professor & Micron Chair Professor
Department of Industrial Engineering & Engineering Management
National Tsing Hua University, Hsinchu 30013, Taiwan
Dr. Chen-Fu Chien is Tsinghua Chair Professor Tsinghua Chair Professor & Micron Chair Professor in the Department of Industrial Engineering & Engineering Management, National Tsing Hua University (NTHU), Taiwan. He also serves as the Convener for Industrial Engineering and Management Program, Ministry of Science & Technology, Taiwan, and as the Director of Artificial Intelligence for Intelligent Manufacturing Systems (AIMS) Research Center that is one of four national AI centers sponsored by MOST, Taiwan, as well as AIMS Fellows Executive Program. Dr. Chien has been a Principal Investigator and the Director for the NTHU-TSMC Center for Manufacturing Excellence in NTHU. From 2005 to 2008 while on leave, he served as the Deputy Director of Industrial Engineering Division in TSMC. Dr. Chien holds 23 invention patents for intelligent manufacturing and has published more than 170 journal papers. Dr. Chien has received many industry awards including the Executive Yuan Award for Outstanding Science & Technology Contribution (2016), the National Quality Award from the Executive Yuan (2012), Distinguished Research Awards (2007, 2011, 2016). He received the 2011 Best Paper Award from the IEEE Trans. on Automation Sciences and Engineering and 2015 Best Paper Award from the IEEE Transactions on Semiconductor Manufacturing.
“Industry 3.5” to Empower Intelligent Manufacturing and Empirical Studies in Taiwan
Leading industrialized countries including Germany and USA have reemphasized the importance of advanced manufacturing via the corresponding national competitive strategies such as Industry 4.0 and AMP. The paradigms of global manufacturing networks for smart production are shifting, in which the increasing adoption of artificial intelligence, multimode sensors and edge computing, intelligent equipment and robotics, Big Data Analytics, and Internet of Things (IOT) have empowered an unprecedented level of manufacturing intelligence. Furthermore, international companies are battling for dominant positions in this new arena of “manufacturing platform”. On the other hand, the industry structures in emerging countries may not be ready for the migration of cyber-physical systems and advanced manufacturing solutions as proposed in Industry 4.0, while also facing other needs to create jobs and maintain economic growth. This study aims to propose “Industry 3.5” as a hybrid strategy between the best practice of existing manufacturing for Industry 3.0 and to-be Industry 4.0. Indeed, the developments of new technologies such as AI, Big Data Analytics also provide opportunities for disruptive innovations to support smart production. A number of empirical studies in high-tech manufacturing and other industries are used for validation. Future research directions are discussed to implement the proposed Industry 3.5 to bridge value propositions of industrial engineering research in the restructuring value chains of global manufacturing networks.
Tokyo Electron Technology Solutions
Mr. Masahide Ozawa is a Technical Consultant within the Technology Solutions & Marketing Division of Tokyo Electron Ltd (TEL) in Tokyo, Japan. Since 2010, he has been responsible for the development of new and next generation device testing equipment. Ozawa-san has also been an active member of the Japan Memory Manufacture Team focused on wafer testing challenges within memory products. Prior to joining Tokyo Electron Technology Solutions, Ozawa-san spent over 20 years gaining broad experience in Wafer Sort (CP) On-Line & Networking System Development, PKG Design, Testing Process Development and Failure Analysis of Semiconductor Devices. Ozawa-san has made numerous industry presentations, contributed to patents, and coauthored presentation at SWTest Conference (San Diego) in 2004, 2005, and 2007. He earned a Master’s Degree in Electronics Engineering from the Kyoto University in Japan.
Wafer Test Value and Future
The Wafer Sort (CP) process is sometimes considered to be a “Non-Value Added Process” however, due to the gathering of “Big Data” during wafer sort , the wafer sort process is now providing critical information used to improve chip design along with the wafer fab process. The amount of Wafer Fab Process Equipment within a Fab represents a large percentage of the investment that is spent by the semiconductor industry. “Big Data” process improvements are key in maintaining consistent yields for high volume Memory Products.
During the past 20 years of Memory Wafer Testing, we can see 2 big technology break-throughs which have provided significant reduced test of cost solutions. The first is implementation of Large Area Multi-DUT Testing and the other has been the Multi-Stage Test System.
To address advance technology nodes, closer cooperation will be required between Test Engineers, ATE Engineers and Probe Card Technologies. With each new technology node, there will be additional challenges beyond PAD Size, Probe Force, Probe Pitch, and, etc.
- Diversification of “Best Testing Technology” will cause the current business model to change. Especially for OSAT, IDM and Applications.
- These new technology nodes will be very temperature sensitive and will require improved thermal management technologies to overcome them.